The present invention relates to timing adjustments in digital integrated circuits, and more specifically, to timing adjustments across transparent latches to facilitate power reduction.
Digital integrated circuits (ICs) or chips include many components to perform processing and storage. One of the primary considerations in the selection and placement of these components is the timing requirements of the chip. Among the chip components, two types of storage elements include non-transparent latches (e.g., flip-flops) and transparent latches. Unlike edge-triggered non-transparent latches, transparent latches are able to transmit data during the period when the clock is active. During static timing analysis, which is used to verify the timing correctness of digital integrated circuits, transparent latches are often analyzed by assuming a discrete cycle boundary within the active clock interval by which a stable value will propagate to the latch output.